The present invention relates to a self-aligned semiconductor fabrication process for fabricating a semiconductor device with dielectrically isolating regions. More specifically, the present invention relaes to a process for forming dielectrically isolating regions having different depths in a semiconductor circuit structure.
Generally, bipolar transistors (which will be called "transistors" hereinafter) fabricated as part of an integrated circuit on a monocrystalline semiconductor substrate, require isolation between the transistors. An isolation technique employing a reverse-biased p-n junction that surrounds an active device area has been used for isolating such transistors from each other. The junction isolation from each other requires a large isolation area and is liable to introduce larger parasitic capacitances than those which ordinarily result from oxide/isolation, a typical example of which is, an isoplanar oxide isolation which is well known in the art. According to this isoplanar oxide isolation technique, a buried collector layer 12 is formed in a silicon body 11, and, then, an epitaxial layer 13 is grown on the silicon body 11 sandwitching the buried collector layer. The silicon body 11, the buried layer 12 and the epitaxial layer 13 constitutes a silicon substrate 100. Using a patterned silicon nitride film 14 as a mask, the epitaxial layer 13 is selectively etched away by alkaline etchant to form groove portions 15A, 15B and 15C as shown in FIG. 1(A). Then, an oxidation process follows. The surfaces of the groove portions are thermally oxidized to obtain isolation oxide 16A, 16B and 16C (See FIG. 1(B)). As a collector contact region is formed between the isolation oxides 16A and 16B, the isolation oxide 16A serves as an base-collector isolation region. On the other hand, the isolation oxides 16B and 16C define an active region where the transistor is fabricated. However, when the width L of each groove is less than square root of the depth D of the groove, the problem is encountered in the conventional technique in that the planarization of the silicon oxide refilled into the etched grooves 16A, 16B and 16C is difficult as shown in FIGS. 2 (A) and 2(B) with a resultant of discrete wiring passing thereon. Further, there is a possibility that the oxidation of the steeply inclined portion of the groove results in occurrrence of crystal defects. For this reason, such a dielectric isolation cannot cover the progress of miniaturization of bipolar transistors.
To overcome this problem, there have been proposed so called trench isolation techniques. For instance, U.S. Pat. No. 3,966,577, U.S. Pat. No. 4,104,086 and U.S. Pat. No. 4,318,751 disclose respective trench type isolation techniques. According to the typical trench type technique, an n+ buried collector layer 32 is formed on the p type body 31, an n- epitaxial layer 33 and a silicon nitride 34 layer being stacked up on the buried collector layer in succession. The silicon body 31, the buried layer 32 and the epitaxial layer 33 constitutes a silicon substate 200. A patterned mask 35 is applied to the silicon nitride layer, then, the silicon nitride layer 34 and the buried collector layer 32 are selectively etched by reactive ion etching technique as shown in FIG. 3(A) so as to form a isolation groove surrounding an active region. After this, the mask 35 is removed. The silicon nitride layer 34 is patterned by etching process using a photoresist 37 as a mask. The epitaxial layer 33 is selectively removed to form a base-collector isolation groove by reactive ion etching technique as shown in FIG. 3(B), the base-collector isolation groove having a depth less than that of the isolation groove surrounding an active region. After the removal of the photoresist 37, the isolation oxides 38 and 39 are thermally grown, thereby refilling the isolation grooves. And if necessary the silicon nitride layer 34 is removed as shown in FIG. 3(C). However, according to the trench technique, a plurality of lithography processes are required to form the isolation grooves in different depth. These successive lithography processes require certain tolerances for mask alignments. These tolerances restrict the enhancement of element density of IC.
As appreciated from the above discussion, when dielectrically isolating regions having at least two different thicknesses are formed in a semiconductor substrate, there exist the following process requirements to be satisfied: First is that miniaturization is possible. Second is that crystal defects are not produced. Third is that good self-alignment nature is insured. Fourth is that the sufface of the isolating region is highly planarized.